A 32nm logic technology featuring 2ndgeneration highk. Then it is necessary to etch the high k dielectric or an sio 2 high k laminate and stop on silicon. Both the oxygen and nitrogen annealing will reduce the gate leakage current without increasing oxide thickness. Chau and colleagues explained the problem that led to the use of a metal gate in detail in highkmetalgate stack and its mosfet characteristics, ieee electron. Selective isotropic wet etching of tin and tan for high k. The equivalent oxide thickness of the highk dielectric has been reduced from 1. As metaloxidesemiconductor fieldeffect transistors mosfets have decreased in size, the thickness of the silicon dioxide gate dielectric has steadily decreased to increase the gate capacitance and thereby drive current, raising device performance. Pdf in this work, we report the use of aluminum ion implantation to modulate the threshold voltage for hfbased highk tin metal gate pmos finfets. The threshold voltages of the devices changed with various pma conditions. Jun 06, 2016 the introduction of high k metal gate stacks guaranteed the trend towards smaller transistor dimensions. Comprehensive electrical characterization and lowfrequency noise characterization were. Then it is necessary to etch the high k dielectric or an sio 2high k laminate and stop on silicon. These new materials along with the right process recipe reduced the nmos gate leakage by 25x and pmos.
More recently, intel introduced in their 32nm technology a slightly different scheme where the highk is deposited last, right before the metal gate electrodes, and after the complete removal of the dummy gates. The improvement of reliability of highkmetal gate pmosfet. First, it is shown that rmg gate stacks used for logic applications need to be seriously reconsidered, because of the additional anneals needed in a dram process. The incorporation of highk dielectrics with metal gates into a manufacturable, high volume transistor process is the result of tremendous ingenuity and effort by many scientists and engineers. From the 45 nm node onward, the metal gate technology returns, together with the use of highdielectric materials, pioneered by intel developments. Gate leakage current, polysilicon gate depletion, boron penetration. From the 45 nm node onward, the metal gate technology returns, together with the use of high dielectric materials, pioneered by intel developments. In transistor gate dielectrics, highk is desirable as it gives high performance with low leakage. Device scaling ofhigh performance mosfet with metal gate. The incorporation of high k dielectrics with metal gates into a manufacturable, high volume transistor process is the result of tremendous ingenuity and effort by many scientists and engineers. Effects of highk dielectric with metal gate for electrical.
Lowpower dramcompatible replacement gate highkmetal gate. Silicon dioxide sio 2 has been used as a gate oxide material for decades. High kmetal gate the technology in an intel chip that enabled the fabrication of 45 nm microprocessors in 2007. Work function tuning in sub20nm titanium nitride tin.
By david lammers qualcomm cdma technologies said it will not use a highkmetal gate hkmg process for most of the chips it makes at the 28 nm node, sticking with a polysion gate stack. Ald highk as a common gate stack solution for nano. The introduction of novel gate stack materials high k metal gate has enabled the resumption of moores law at the 4532nm nodes, when conventional polysion gate stacks ran out of steam. Some of the samples were annealed at 400c and 450c in oxygen or nitrogen ambient for. The oxygen and nitrogen were shown to diffuse through the tin layer in the highkmetal gate devices during pma. With a high k material as gate dielectric, effective oxide thickness eot can be further scaled down without increasing gate tunneling leakage. This marked the return of metal gate technology on silicon for the first time since polysilicon gates. Intel corporations announcement of a replacement gate build strategy for highk metal gate technology in their 45 nm device node has inspireddesigns for the sub.
The candidates for the metal gate electrode are probably, for nmos, ta, tan, nb single metal gate and for pmos wnruo 2 the pmos metal gate is normally composed by two layers of metal. Highkmetal gate article about highkmetal gate by the. Lowpower dramcompatible replacement gate highkmetal. May 11, 2017 once youve replace the sio2 gate oxide with highk dielectrics hafnium oxide or zirconium oxide you band diagram is completely different. Work function tuning in sub20nm titanium nitride tin metal. The 28nm process technology is slated to become the foundation for a new. In this work, the possibility of integration of high k metal gate hkmg, replacement metal gate rmg gate stacks for low power dram compatible transistors is studied. Both provide twice the gate density of comparable 40nm processes and an sram cell size shrink.
Dec 17, 2004 nec today announced the development of a transistor featuring a new gate stack structure using a hfbased high k dielectric 1 and a metal gate electrode 2, which simultaneously realizes. Device scaling ofhigh performance mosfet with metal gate high. High k \ metal gate stack shows significantly lower gate leakage than sio2. Therefore, the gate leakage current can be suppressed by using highk materials, which means that the physical thickness of highk films can be thicken without changing eot.
Similarly, on the most advanced technology nodes that use highk dielectric and metal gate in the gate stacks, the sonos transistor will exploit all the key benefits from these new features. Reliability of highk metal gate fieldeffect transistors. Brief contents i gate basics 3 1 introduction 5 2 installing and running gate 27 3 using gate developer 35 4 creole. Development of transistor with new metal gate electrode. The introduction of highk metal gate stacks guaranteed the trend towards smaller transistor dimensions. As elements in the chip were being reduced to 45 nanometers, the gate dielectric began to lose its insulating dielectric quality and exhibited too much leakage. Ald highk as a common gate stack solution for nanoelectronics. Cmp solutions for the integration of high k metal gate. Jul 08, 2008 animation of intels new high k metal gate mosfet. Highkmetal gate interfacethe highkmetal gate interfacial layer can be either an insulating layer or a conductive layer. Nec today announced the development of a transistor featuring a new gate stack structure using a hfbased highk dielectric 1 and a metal gate electrode 2, which simultaneously realizes. Lowk dielectric lowk dieletrics are used to insulate onchip interconnects and should not be confused with the highk dielectrics. Intel made a significant breakthrough in the 45nm process by using a high k hi k material called hafnium to replace the transistors silicon dioxide gate dielectric, and by using new metals to replace the n and pmos polysilicon gate electrodes.
From this study, we find the suitable combination materials between the highk and metal gate, and how it is a good affected on the electrical. A novel flat band voltage tuning for metalhighk gate stack. However, different schemes to integrate those novel materials have been recently proposed, traditionally referred to as gate first and gate last. These new materials along with the right process recipe reduced the nmos gate.
Lowfrequency noise in highk gate stacks with interfacial. Keywords18 nm nmos, highk dielectric, metal gate, silvaco. These devices vary in the highk material, highk thickness, highk deposition method and interlayer material. High k \ metal gate stack achieves nmos and pmos channel mobility close to sio2s. After interfacial sio 2 layerhighk and tin deposition, tin layer was then deposited with the thickness of 100200 a. The cypress sonos technology currently offers multiple cell options to fit into different applications, trading off cell and macro sizes for access time. The contents firstly include the deposition of zirconium dioxide and hafnium dioxide from the gas phase, using organometallic precursors, and their physicochemical characterization. In interconnects, lowk is desirable as it leads to faster signal transmission times. In an rmg integration scheme, a polysi capped dummy gate stack is first deposited, featuring in a highk first scheme hkf, used in this work a sio 2 interfacial layer ilhighk stack followed by an etch stop layer esl. The interfaces of lanthanum oxidebased subnanometer eot. The company described the rationale behind the strategy, which because of qualcomms size will have a major impact on the foundry business, at the 2010. In addition, the gate leakage current can also be suppressed by using large band gap. Given the requirement for an amorphous highk gate dielectric, the ranking of hfo2 as a desired highk gate dielectric drops considerably, because it tends to crystallize at a relatively c 6. More recently, intel introduced in their 32nm technology a slightly different scheme where the high k is deposited last, right before the metal gate electrodes, and after the complete removal of the dummy gates.
The implementation of hfo2, as highk dielectric, also lead to a substantial number of manufacturing and reliability challenges. In order to tune the work function, one or several metal layers are then deposited. After the high temperature sd and silicide annealing cycles, the dummy gate was removed and metal gate electrodes were deposited last. By ruben ghulghazaryan, jeff wilson, and ahmed abouzeid feol cmp modeling helps designers and foundries predict cmp hotspots in advanced node designs for decades, semiconductor manufacturers have used chemicalmechanical polishing cmp as the primary technique for the smoothing and leveling.
Also, using metal as a gate electrode mg, the polysilicon gate pg depletion effect is. Why is a metal used instead of polysilicon for highk gate. Selective isotropic wet etching of tin and tan for high k metal gate structure. Work functions for nmos and pmos breakthroughs with metal gates ntype metal and ptype metal with the correct work functions on highk have been engineered. The introduction of novel gate stack materials highkmetal gate has enabled the resumption of moores law at the 4532nm nodes, when conventional polysion gate stacks ran out of steam. Highk\metalgate stack shows significantly lower gate leakage than sio2. After the hightemperature sd and silicide annealing cycles, the dummy gate was removed and metal gate electrodes were deposited last. These devices vary in the high k material, high k thickness, high k deposition method and interlayer material. Nov 14, 2007 intel 45nm high k metal gate press release 1. Highk hk dielectrics are a solution to overcome these limitations. Pdf highk metalgate pmos finfet threshold voltage tuning.
The implementation of hfo2, as high k dielectric, also lead to a substantial number of manufacturing and reliability challenges. In some cases the gate electrode may be composed of two layers of metal, e. Work functions for nmos and pmos breakthroughs with metal gates ntype metal and ptype metal with the correct work functions on high k have been engineered. Ufc 402203 security fences and gates whole building design. The evolution of highk metal gate transistors, from the first planar 45nm to the latest 14nm node. The fabrication process of the highk metal gate last device was sketched in figure 1. Intel made a significant breakthrough in the 45nm process by using a highk hik material called hafnium to replace the transistors silicon dioxide gate dielectric, and by using new metals to replace the n and pmos polysilicon gate electrodes. Since then titanium nitride tin metal gates work function wf tunability with its thickness thickness increases, work function increases is a. Recent trend from topdown lithography to selfalignment and bottomup patterning approaches source. The present work addresses the investigation of high. The reliability of the devices, especially for the oxygen annealed devices, was. Dielectric breakdown in a 45 nm highkmetal gate process.
With a highk material as gate dielectric, effective oxide thickness eot can be further scaled down without increasing gate tunneling leakage. Once youve replace the sio2 gate oxide with highk dielectrics hafnium oxide or zirconium oxide you band diagram is completely different. Schematic is my graphical representation of an idea in the presentation by g. Highk materials and metal gates for cmos applications. First it is necessary to etch gate metal for nmos and pmos devices, stopping on the high k dielectric. A novel flat band voltage tuning for metalhighk gate. In order to overcome this problem, one may add al in hfo2 to form. Designing into a foundry lowpower highk metal gate 28nm cmos solution. High k hk dielectrics are a solution to overcome these limitations. Thus to address these challenges, highkmetal gate stack has been introduced in commercially available microprocessors from 2007. Role of highk gate dielectrics and metal gate electrodes.